Semiconductor integrated circuits are typically fabricated by a layering process in which several layers of material are fabricated on or in a surface of a wafer, or alternatively, on a surface of a previous layer. This fabrication process typically requires subsequent layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be uneven due to an uneven topography associated with an underlying layer. As a result, a layer may need to be polished in order to present a smooth, planar surface for a subsequent processing step. For example, a layer may need to be polished prior to formation of a conductor layer or pattern on an outer surface of the layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the wafer. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates, along with the selective removal of materials fabricated on the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
In these polishing processes, it is often important to determine an endpoint of the polishing process. Overpolishing (removing too much) of a conductive layer results in increased circuit resistance and potential scrapping of the semiconductor wafer. Since many processing steps have occurred prior to the polishing process, scrapping a semiconductor wafer during fabrication may undesirably result in significant financial loss. Underpolishing (removing too little) of a conductive layer on the other hand leads to failure in isolating circuits and results in electrical shorts. Presence of such electrical shorts leads to rework (redoing the CMP process) thereby disadvantageously increasing costs (e.g. production costs) associated with the semiconductor wafer. Thus, a precise endpoint detection technique is needed.
A typical method employed for determining the endpoint in polishing systems is to measure the amount of time needed to planarize a first wafer, and thereafter polishing the remaining wafers for a similar amount of time. In practice this method is extremely time consuming since machine operators must inspect each wafer after polishing. In particular, it is extremely difficult to precisely control the removal rate of material since the removal rate may vary during the polishing of an individual wafer. Moreover, the removal rate may be diminished in the process of polishing a number of wafers in sequence.
Another method employed for determining endpoint in polishing systems is to form a polishing endpoint layer in the semiconductor device, and thereafter polish the semiconductor device down to the polishing endpoint layer. To this end, polishing systems detect when the polishing process reaches the polishing endpoint layer and terminate the polishing process in response to reaching the polishing endpoint layer. Various techniques have been used to detect when the polishing process reaches the polishing endpoint layer. For example, techniques have heretofore been utilized which first deposit a chemically detectable endpoint layer on the semiconductor at the desired level and thereafter polish the semiconductor wafer until the material associated with the endpoint layer is chemically detected by known chemical analysis devices. However, such techniques have a number of drawbacks associated therewith. For example, chemical analysis endpoint detection techniques which have heretofore been designed generally cannot be utilized during a shallow trench isolation (STI) process. This is true since materials which have heretofore been used as the endpoint layer are typically electrochemically reactive with either the silicon substrate, the active areas of the semiconductor wafer, or the materials of the various layers within the semiconductor wafer thereby preventing use thereof during the shallow trench isolation process.
Moreover, materials which have heretofore been used as the endpoint layer typically require additional fabrication steps in order to deposit the same on the semiconductor wafer thereby undesirably increasing costs associated with the semiconductor wafer. In particular, during the shallow trench isolation process, trenches are generally etched into a silicon substrate having a insulating layer, such as silicon nitride, deposited thereon. After the trenches have been etched into the wafer, the trenches are filled with a second insulating layer, such as silicon dioxide, and thereafter the wafer is polished to a desired level or thickness. More specifically, it is desirable to polish the wafer down to the first insulating layer of silicon nitride. However, materials which have heretofore been used as a polishing endpoint layer, such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or arsenosilicate glass (AsSG), would undesirably require the wafer to be moved between a number of work tools in order to deposit the same on the wafer. For example, the wafer is initially positioned in a first work tool to deposit the first insulating layer of silicon nitride on the wafer. Thereafter, the wafer must be removed from the first work tool and placed in a second work tool for deposition of the polishing endpoint layer (e.g. BPSG). Thereafter, the wafer must be returned to the first work tool for subsequent processing of the wafer.
Moreover, such glass materials (BSG, PSG, BPSG, and AsSG) are electrochemically active with existing structures within the semiconductor wafer. In particular, use of such glass materials within close proximity to the silicon substrate may undesirably cause doping of the substrate. Hence, such glass materials are generally not suitable for use as the polishing endpoint layer in a shallow trench isolation process.
Thus, a continuing need exists for a method which accurately and efficiently detects when a polishing system polishes a semiconductor device down to a desired polishing endpoint layer. Moreover, a continuing need exists for a method which accurately and efficiently detects when a polishing system polishes a semiconductor device down to a desired polishing endpoint layer which is not electrochemically reactive with the components of the semiconductor wafer.